USB 3.0 offers a signaling rate of 5 Gbps, more than 10 times the 480 Mbps of USB 2.0. In practical terms, that means much more data can move through the connection in the same amount of time. That speed is what makes it so useful, but it also makes PCB routing more challenging. At 5 Gbps, the PCB itself becomes part of the signal path, and layout mistakes that USB 2.0 would tolerate can break the link or silently drop it back to 480 Mbps.
One example of our USB 3.0 work was a custom carrier board for a PHYTEC i.MX-based design. The board was small and used an HDI stackup, which made several of these decisions harder. This blog covers the key considerations that made it work, and they apply to almost any USB 3.0 layout.
Figure: Custom carrier board layout
Controlled Impedance on the Differential Pairs
USB 3.0 uses one transmit pair and one receive pair. A Type-C connector has four pairs, two TX and two RX, so the plug works both ways up. Only one TX and one RX pair are used at a time. These pairs are routed for a target differential impedance of 90 ohms, because at 5 Gbps, each bit is only 200 picoseconds wide, and reflections from impedance changes can quickly reduce the available signal margin. Reflections occur when part of the signal bounces back after encountering a change in impedance. They are important because they can distort the signal, making it harder for receiver to distinguish between a 0 and 1.
Impedance depends on trace width, spacing, and the stackup, so we defined all three together and confirmed them with the PCB fabricator before routing a single trace. On an HDI board with thin dielectrics, the required geometry comes out narrower than typical, so assuming standard values is an easy way to miss 90 ohms without knowing it. PCB design tools can be used to calculate the expected impedance during layout, which can then be verified by the manufacturer during fabrication.
Length Matching Within Each Pair
USB 3.0 carries each high-speed signal over two traces that work together as a differential pair. These two traces carry opposite versions of the same signal and are interpreted together by the receiver.
Figure: USB 3.0 Differential Pair Routing
Intra-pair matching means keeping these two traces nearly the same length so their signals arrive at almost the same time. We kept this mismatch, or skew, within a few mils and applied length compensation close to where the mismatch occurred, typically at the pin breakout. We routed the two traces within each pair side by side with symmetric geometry and kept bends at 45 degrees.
Inter-pair matching, by contrast, means matching the length of one differential pair to another. In USB 3.0, the transmit (TX) and receive (RX) pairs carry independent data streams, so they do not need to be length-matched to each other.
Figure: Intra-pair vs. inter-pair skew
Keeping the Ground Plane Unbroken
When a high-speed signal travels along a PCB trace, an associated current flows back through the nearby reference plane. This is called the return current, and at high frequencies it tends to follow a path close to the signal trace. We therefore routed the SuperSpeed pairs over a continuous ground reference and never crossed a plane split, which would force the return current into a detour that increases emissions and coupling. At every layer change, we placed ground stitching vias next to the signal vias so the return current could maintain a short path.
Minimizing Vias and Stubs
Every via at 5 Gbps introduces a discontinuity that can disturb the controlled impedance and cause reflections, as explained earlier. Our board’s small size and HDI stackup forced the SuperSpeed pairs onto inner layers. We kept the pairs referenced to continuous planes, maintained the required trace geometry, and chose layers that required as few transitions as possible.
We also avoided long via stubs, the unused portions of a via beyond the signal’s destination layer, which can cause additional reflections. Blind vias connect an outer layer to an inner layer without passing through the entire board. Microvias make short connections between nearby layers. Both can help reduce or eliminate these unused stubs.
Keeping Noisy Signals Away
Crosstalk into a 5 Gbps lane is difficult to address after fabrication, so we kept the SuperSpeed pairs well away from clocks, switching regulators, and other busy signals. Keeping enough physical separation between these signals reduces unwanted coupling and helps preserve signal integrity. USB 3.0 can also add noise in the 2.4 GHz band, so keep the pairs and connector away from Wi-Fi and Bluetooth antennas.
Selecting Low-Capacitance ESD Protection
ESD protection sits directly on the data lines, so the device itself becomes part of the signal path. Adding an ESD device also adds capacitance to the line. If that capacitance is too high, it loads the high-speed signal and slows its edges, which can degrade signal quality at 5 Gbps. We therefore selected ESD devices designed for USB 3.0 with very low capacitance per line and placed them close to the connector, so a strike is clamped before additional trace inductance allows the voltage to rise further.
Figure: USB Type-C schematic
Before You Route USB 3.0
Before routing USB 3.0, it helps to work through the key decisions in order:
- Plan your USB 3.0 routes first and place your components accordingly.
- Verify the trace width, trace gaps with the manufacturer or a PCB calculator tool before you begin routing
- Route each SuperSpeed differential pair together and keep the two traces within each pair closely length-matched.
- Keep a continuous ground reference beneath the pairs and avoid routing across plane splits.
- Minimize vias and layer changes to reduce impedance discontinuities and avoid unnecessary via stubs.
- Keep the SuperSpeed pairs away from noisy signals such as clocks and switching regulators.
- Choose low-capacitance ESD protection suitable for USB 3.0 and place it close to the connector.
- Consider EMI and antenna placement early, particularly when Wi-Fi or Bluetooth operates nearby.
Getting these decisions right before routing begins can prevent much more difficult signal-integrity and EMI problems after fabrication.
If you are working on a project with USB 3.0 or any high-speed interface and running into signal integrity issues, we are happy to help. Feel free to Contact Us for PCB layout, high-speed hardware design, and firmware development support.
