Designing impedance-controlled PCBs for USB, HDMI, or MIPI starts before routing. You need to choose a suitable stackup and agree on trace dimensions that the manufacturer can reliably produce.
When signal transitions are fast enough, a PCB trace needs to be treated as a transmission line rather than simply a connection between two points.
Trace width, pair spacing, and distance from the reference plane all affect impedance. Changes along the route can cause signal reflections, leading to ringing, overshoot, or communication errors.
In this guide, we walk through the process step by step, from identifying the required impedance and choosing a stackup to routing the signals and verifying the manufactured board.
Identify the Signals and Their Requirements
Begin by identifying which signals need controlled impedance. Use the interface specification and the hardware design guidelines for the components in your design to establish the targets.
Common examples include:
| Interface | Typical impedance target |
| USB 2.0 | 90 Ω differential |
| Ethernet | 100 Ω differential |
| PCIe | 85 Ω differential |
| HDMI | 100 Ω differential |
| MIPI D-PHY | Typically 100 Ω differential |
| RF signals | Commonly 50 Ω single-ended |
These are starting points. Check the requirements for the particular interface and devices, including the permitted impedance tolerance, timing constraints, and routing guidance.
Once these requirements are known, define PCB design rules for each high-speed interface.
Agree on a Stackup with the PCB Manufacturer
Trace width alone does not determine impedance. The result also depends on:
- Copper thickness
- Distance to the reference plane
- Dielectric constant of the PCB material
- Trace position within the stackup
- Solder mask and nearby copper
- Spacing between traces in a differential pair
This is why a trace width that produces the correct impedance on one PCB may give a different result on another.
Before finalizing the routing geometry, ask the intended manufacturer for a suitable stackup. Discuss the available materials, dielectric thicknesses, finished copper thicknesses, and practical trace widths and spacings.
Figure: Six-layer PCB stackup with copper and dielectric thicknesses
This project example shows a six-layer PCB stackup. Copper thickness, dielectric properties, and the distance between a signal layer and its reference plane all affect trace impedance.
Choosing that construction early helps avoid a common problem: discovering during layout that the required impedance demands traces that are too narrow or expensive to manufacture.
Calculate a Manufacturable Trace Geometry
With the proposed stackup in place, use an impedance calculator or, preferably, a field solver to determine the required geometry.
For a single-ended microstrip, the main inputs include trace width, copper thickness, distance to the reference plane, and dielectric constant. For a differential pair, the spacing between the traces also matters.
In this design, the top-layer routing rule specifies a trace width of 0.125 mm and a pair gap of 0.127 mm. These dimensions are specific to the design and should not be copied into another PCB without recalculation.
Check the result against the manufacturer’s capabilities before accepting it.
Suppose the calculation requires a 0.075 mm trace, but the manufacturer recommends a minimum of 0.10 mm for the intended production process and cost. Revisit the stackup rather than forcing the layout to use the narrower trace.
Possible adjustments include changing the dielectric thickness, copper thickness, routing layer, pair spacing, material, or fabrication technology. Recalculate after each change until the electrical target and manufacturing requirements work together.
Turn the Agreed Geometry into PCB Rules
Once the geometry has been reviewed with the manufacturer, enter it into the PCB design software.
Set the relevant constraints for each signal class, including:
- Routing width and permitted layers
- Differential-pair spacing
- Clearance to other signals
- Length and skew limits where required
Figure: Differential-pair routing rules linked to an impedance profile
Use these rules throughout the layout so that controlled-impedance nets are routed consistently.
Route with a Continuous Return Path
A correctly sized trace still needs a suitable reference plane.
For a high-speed signal routed over ground, the high-frequency return current tends to follow the signal closely in the plane beneath it. A split, cutout, or large void interrupts that path and forces the return current to take a detour.
Maintain a continuous reference plane underneath the high-speed route whenever possible.
This check deserves as much attention as the trace dimensions. A route can meet its width and spacing rules while still passing over a gap in the reference plane.
Manage Discontinuities and Layer Changes
Preserve the calculated geometry along the route as far as practical. Changes in trace width, pair spacing, reference-plane distance, or nearby copper can change the local impedance.
Pay particular attention to connectors, component pads, BGA breakouts, test points, and ESD protection devices. Every real PCB has discontinuities; the aim is to limit their size and electrical length.
Layer changes also need review. Signal vias introduce parasitic capacitance and inductance, and unused via barrels can form stubs.
Minimize unnecessary transitions. If a signal changes reference planes, the return current also needs a path between those planes. Depending on the stackup and interface, carefully positioned ground stitching vias may be required close to the signal vias.
For more demanding links, via structures may need further analysis. Back-drilling, blind vias, buried vias, or microvias may be appropriate depending on the signal bandwidth, board thickness, and loss budget.
Check Differential Pairs Beyond Length Matching
Equal trace lengths are only one part of differential-pair routing.
Also check the pair’s impedance, spacing, symmetry, reference-plane continuity, and exposure to nearby signals. Avoid unnecessary separation of the two traces and keep their paths reasonably balanced through transitions and component connections.
Apply length and skew limits from the interface requirements. Adding excessive serpentine routing simply to make two displayed lengths identical can introduce extra coupling and discontinuities.
Nearby signals can couple energy into the differential pair as crosstalk. Set clearance to neighboring signals according to the design’s signal-integrity requirements.
The image shows meanders used to adjust trace length; use only as much extra routing as the timing requirements need.
Figure: Meandered PCB traces for length adjustment
Specify What the Manufacturer Must Build
An impedance value in the CAD tool does not automatically become a fabrication requirement.
Include a controlled-impedance table in the manufacturing documentation. Identify the relevant layers and nets, transmission-line structure, and target impedance. Reference the agreed stackup and its associated trace widths and pair gaps.
For example:
| Layer | Nets | Structure | Target impedance |
| L1 | USB_DP / USB_DM | Differential microstrip | 90 Ω |
| L1 | RF_ANT | Single-ended microstrip | 50 Ω |
The fabricator may need to compensate for etching, plating, and material tolerances to achieve the target.
Verify the Manufactured Result
Where required, arrange impedance testing with the manufacturer before production.
Test coupons contain transmission-line structures made using the same manufacturing process as the board. The manufacturer can measure these structures using Time Domain Reflectometry, or TDR, to check their impedance against the specified limits.
For a 90 Ω target with a ±10% tolerance, the acceptable range would be 81 Ω to 99 Ω. Choose the tolerance according to the interface and project requirements rather than assuming ±10% applies to every design.
Conclusion
The calculation itself is usually the easy part. The engineering work is making sure that the impedance you calculated is still the impedance that exists after the PCB has been manufactured.
That is why we involve the PCB manufacturer early, build the layout around an agreed stackup, document the impedance requirements explicitly, and verify them during fabrication when the application requires it.
If you are working on a project with high-speed interfaces and need help with controlled-impedance PCB design or signal integrity issues, we are happy to help. Feel free to Contact Us for PCB stackup planning, PCB layout, and high-speed hardware design support.
References
- Texas Instruments, High-Speed USB Layout Guidelines
- Altium, Interactively Routing Controlled Impedance
- Altium, PCB Manufacturing and Impedance Control
- Siemens EDA, Etch Effects in Impedance Calculations
- Altium, PCB Fabrication Drawings and Impedance Coupons
