Project Overview
One of our clients needed a connected device with an OLED display. The display was an important part of the device’s user interface.
During testing of the first prototype, the display initialized but did not produce the expected video output. In some cases, the screen remained blank, while in others it showed unexpected visual artifacts. Finding the cause required us to investigate both the hardware and firmware sides of the MIPI DSI link.
The Problem
The first step was to investigate the different parts of the display interface that could be contributing to the failure.
We reviewed the display configuration, register settings, power sequencing and management, and the hardware around the MIPI interface. This investigation pointed to multiple areas that needed closer attention rather than a single isolated cause.
That led us to look deeper into the PCB implementation, the display’s power requirements, and the firmware controlling the MIPI interface.
Figure: OLED display showing visual artifacts
Root Cause 1: MIPI Routing Without Controlled Impedance
Why controlled impedance was initially skipped
The MIPI DSI interface in this device was running at a relatively low data rate. During the first PCB layout, we assumed that controlled impedance would not be necessary at this speed. So the MIPI lanes were routed as ordinary traces, which also helped us complete the first prototype faster.
The problem was that data rate was not the only factor that mattered.
Why controlled impedance still mattered
MIPI D-PHY uses low-voltage differential signaling in high-speed mode. Although the interface was running at a lower data rate, the signal edges were still fast because their characteristics are determined by the PHY.
A lower data rate means there is more time between bits, but it does not necessarily mean that each electrical transition is slow. With fast signal edges, the PCB traces still need to maintain the required impedance.
Because the MIPI lanes on the first PCB were not routed with controlled impedance, impedance discontinuities caused reflections that degraded signal quality and contributed to the display failing to produce the expected output.
So while the lower data rate provided more timing margin, it did not remove the need for proper controlled-impedance routing.
Root Cause 2: Power Sequencing / Power Management
Another issue was the display power-up sequence. The display required multiple power rails that could not simply be enabled at the same time.
In the first implementation, the required sequencing between these rails had been overlooked. The 3.3 V supply needed to be enabled first, followed by the positive OLED supply at +ELVDD. After a delay of approximately 10 ms, the negative OLED supply at −ELVSS could then be enabled.
Instead, these supplies were initially being enabled together. Following the required sequence was important not only for proper display operation but also to reduce the risk of damaging the OLED.
The power-up sequence was therefore corrected so that each rail was enabled in the required order with the appropriate delay.
Root Cause 3: LP-to-HS Transition Timing
During firmware debugging, we found another problem in the transition between the MIPI D-PHY operating modes.
D-PHY uses Low-Power (LP) mode for certain states and High-Speed (HS) mode for high-speed data transmission. Moving from LP to HS requires specific timing to ensure the PHY is ready before high-speed communication begins.
In our implementation, the LP-to-HS transition timing was not correct. High-speed communication was starting before the required timing conditions were met, which contributed to the display failing to produce the expected video output.
This meant that addressing the hardware and power-related issues alone was not enough. The firmware timing also needed to be corrected for the display link to operate properly.
The Solution
Hardware
The PCB was respun with the MIPI interface routed with proper controlled impedance. On the revised board:
- The high-speed data lanes and clock lane were routed as 100-ohm differential controlled-impedance pairs based on the actual PCB stackup.
- The traces within each differential pair were length-matched, with lane-to-lane timing requirements also considered during routing.
- The target impedance was confirmed with the PCB manufacturer before ordering the controlled-impedance build.
These changes provided a more consistent transmission path for the MIPI signals and reduced the reflections caused by the original routing.
Figure: PCB layout showing the MIPI DSI lanes after the fix
Power Sequencing
The display power-up sequence was also corrected. Instead of enabling the power rails together, the 3.3 V supply was enabled first, followed by the +ELVDD OLED supply. After a delay of approximately 10 ms, the −ELVSS OLED supply was enabled.
Figure: Oscilloscope showing the power rail sequencing delay
The experience also changed how we approach high-speed interfaces. For MIPI, USB, Ethernet, HDMI, and similar interfaces, we now consider controlled impedance and the PCB stackup from the beginning of the layout rather than making that decision based only on the intended data rate.
Firmware
The firmware was updated to correct the LP-to-HS transition timing, ensuring that the required timing conditions were met before high-speed communication began. This was achieved by adding an acknowledgment in the firmware for the LP-to-HS transition.
We also now consider PHY transition timing as part of the initial firmware implementation rather than something to address during debugging.
Results
With these changes in place, the display began producing the expected video output. The hardware respin addressed the signal integrity problem, the power-up sequence was corrected, and the firmware update fixed the LP-to-HS transition timing. The blank screen and visual artifacts seen on the first prototype were no longer present.
Figure: OLED display showing the expected output
FAQ
Why does controlled impedance matter even at a low MIPI data rate?
A lower data rate does not necessarily mean slower signal edges. In MIPI D-PHY, the electrical characteristics of the high-speed signals are determined by the PHY. Fast signal edges can still be affected by impedance mismatches in the PCB traces, causing reflections that affect signal quality. This is why controlled impedance still matters even when the interface is operating at a relatively low data rate.
Why could the display initialize but still fail to show video?
Display initialization does not guarantee that the MIPI DSI link is operating correctly. In our case, problems with signal integrity, power sequencing, and LP-to-HS transition timing affected the interface even though the display itself was able to initialize.
What is the LP-to-HS transition in MIPI D-PHY?
MIPI D-PHY uses Low-Power (LP) mode for certain states and High-Speed (HS) mode for high-speed data transmission. Moving from LP to HS requires a defined transition sequence and timing. If that timing is not handled correctly, high-speed communication may not start reliably.
If you are working on a project with MIPI displays or any high-speed interface and running into stability issues, we are happy to help. Feel free to Contact Us for hardware design, PCB layout, and firmware development support.
